1. Field of the Invention
The present application relates to an array substrate for a liquid crystal display device, and more particularly, to an array substrate for an in-plane switching mode liquid crystal display device and a method of fabricating the array substrate.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device uses the optical anisotropy and polarization properties of liquid crystal molecules in a liquid crystal layer to display images. Since the liquid crystal molecules have thin and long shapes, the polarization of light through the liquid crystal molecules varies with the alignment direction of the liquid crystal molecules. Accordingly, the LCD device displays an image by controlling the alignment of the liquid crystal molecules as well as the transmittance of light through the liquid crystal layer due to adjustment of the electric field applied to the liquid crystal layer. Active matrix liquid crystal display (AM-LCD) device where thin film transistors (TFTs) and pixel electrodes are disposed in matrix has been the subject of recent researches because of its superiority in displaying moving images and high contrast ratio.
A twisted nematic (TN) mode LCD device includes upper and lower substrates facing each other and a liquid crystal layer therebetween. A common electrode is formed on the upper substrate, which is referred to as a color filter substrate, and a pixel electrode is formed on the lower substrate, which is referred to as an array substrate. When a voltage is applied to the common electrode and the pixel electrode, a vertical electric field is generated between the common electrode and the pixel electrode, and the liquid crystal layer is driven by the vertical electric field. Although the TN mode LCD device has advantages in transmittance and aperture ratio, the TN mode LCD device has disadvantages in viewing angle.
To solve the above problems, an in-plane switching (IPS) mode LCD device having an excellent property in viewing angle has been suggested.
FIG. 1 is a plan view showing an array substrate for an in-plane switching mode liquid crystal display device according to the related art. In FIG. 1, a gate line 20 and a data line 30 are formed on a substrate 10. The gate line 20 and the data line 30 cross each other to define first and second pixel regions P1 and P2. In addition, a common line 50 parallel to the gate line 20 and first and second common electrodes 81 and 82 connected to the common line 50 are formed on the substrate 10. The first common electrode 81 includes a first common horizontal portion 81a and a plurality of first common vertical portions 81b, and the second common electrode 82 includes a second common horizontal portion 82a and a plurality of second common vertical portions 82b. The first common horizontal portion 81a is connected to the common line 50 through a first common contact hole CMH1 and the plurality of first common vertical portions 81b perpendicularly extend from the first common horizontal portion 81a. Similarly, the second common horizontal portion 82a is connected to the common line 50 through a second common contact hole CMH2 and the plurality of second common vertical portions 82b perpendicularly extend from the second common horizontal portion 82a. 
First and second thin film transistors (TFTs) T1 and T2 each connected to the gate line 20 and the data line 30 are formed in the first and second pixel regions P1 and P2, respectively. The first TFT T1 includes a first gate electrode 25a, a first semiconductor layer (not shown) over the first gate electrode 25a, a first source electrode 32a connected to the data line 30 and a first drain electrode 34a spaced apart the first source electrode 32a. Similarly, the second TFT T2 includes a second gate electrode 25b, a second semiconductor layer (not shown) over the second gate electrode 25b, a second source electrode 32b connected to the data line 30 and a second drain electrode 34b spaced apart the second source electrode 32b. The first semiconductor layer includes a first active layer of intrinsic amorphous silicon (a-Si:H) and a first ohmic contact layer of impurity-doped amorphous silicon (n+a-Si:H), and the second semiconductor layer includes a second active layer of intrinsic amorphous silicon (a-Si:H) and a second ohmic contact layer of impurity-doped amorphous silicon (n+a-Si:H).
Further, first and second pixel electrodes 71 and 72 are formed in the first and second pixel regions P1 and P2, respectively. The first pixel electrode 71 is connected to the first drain electrode 34a through a first drain contact hole CH1, and the second pixel electrode 72 is connected to the second drain electrode 34b through a second drain contact hole CH2. The first pixel electrode 71 includes a first pixel horizontal portion 71 a contacting the first drain electrode 34a and a plurality of first pixel vertical portions 71b perpendicularly extending from the first pixel horizontal portion 71a. Similarly, the second pixel electrode 72 includes a second pixel horizontal portion 72a contacting the second drain electrode 34b and a plurality of second pixel vertical portions 72b perpendicularly extending from the second pixel horizontal portion 72a. 
FIG. 2 is a cross-sectional view, which corresponds to a line II-II of FIG. 1, showing an in-plane switching mode liquid crystal display device according to the related art. In FIG. 2, first and second substrates 5 and 10 face and are spaced apart from each other, and a liquid crystal layer 15 is interposed between the first and second substrates 5 and 10. The first and second substrates 5 and 10 include a display area AA and a non-display area NAA. A black matrix 12 shielding light is formed on an inner surface of the first substrate 5 in the non-display area NAA. A color filter layer 16 and an overcoat layer 18 are sequentially formed on the black matrix 12. The color filter layer 16 includes a red color filter 16a, a green color filter 16b and a blue color filter (not shown).
A gate line 20 (of FIG. 1), a first gate electrode 25a (of FIG. 1) and a second gate electrode 25b (of FIG. 1) are formed on the second substrate 10. A gate insulating layer 45 is formed on the gate line 20, the first gate electrode 25a and the second gate electrode 25b. A data line 30 is formed on the gate insulating layer 45. The data line 30 crosses the gate line 20 to define first and second pixel regions P1 and P2. A passivation layer 55 is formed on the data line 30. A plurality of first common vertical portions 81b of a first common electrode 81 (of FIG. 1) and a plurality of first pixel vertical portions 71b of a first pixel electrode 71 (of FIG. 1) are formed on the passivation layer 55 in the first pixel region P1. In addition, a plurality of second common vertical portions 82b of a second common electrode 82 (of FIG. 1) and a plurality of second pixel vertical portions 72b of a second pixel electrode 72 (of FIG. 1) are formed on the passivation layer 55 in the second pixel region P2. The plurality of first common vertical portions 81b and the plurality of first pixel vertical portions 71b alternate with each other in the first pixel region P1, and the plurality of second common vertical portions 82b and the plurality of second pixel vertical portions 72b alternate with each other in the second pixel region P2.
In the first pixel region P1, when a first common voltage and a first pixel voltage are applied to the plurality of first common vertical portions 81b and the plurality of first pixel vertical portions 71b, a first horizontal electric field E1 is generated between the first common vertical portion 81b and the first pixel vertical portion 71b, and liquid crystal molecules 14 of the liquid crystal layer 15 are controlled by the first horizontal electric field E1 such that light of a backlight unit is transmitted through the liquid crystal layer 15 with a first transmittance. In the second pixel region P2, when a second common voltage and a second pixel voltage are applied to the plurality of second common vertical portions 82b and the plurality of second pixel vertical portions 72b, a second horizontal electric field E2 is generated between the second common vertical portion 82b and the second pixel vertical portion 72b, and liquid crystal molecules 14 of the liquid crystal layer 15 are controlled by the second horizontal electric field E2 such that light of the backlight unit is transmitted through the liquid crystal layer 15 with a second transmittance. As a result, the IPS mode LCD device displays a color image.
However, since a vertical electric field instead of a horizontal electric field is generated in an electrode portion F over each of the plurality of first common vertical portions 81b, the plurality of first pixel vertical portions 71b, the plurality of second common vertical portions 82b and the plurality of second pixel vertical portions 72b, the liquid crystal molecules 14 in the electrode portion F can not be horizontally rotated and a required transmittance is not obtained in the electrode portion F. Accordingly, total transmittance and aperture ratio of the IPS mode LCD device are deteriorated.